The present invention relates to semiconductor memories with a high-speed operation and particularly to a dynamic monolithic memory of complementary type including an N-channel field-effect transistor and a P-channel field-effect transistor.
Recently, a dynamic memory using memory cells each of which comprises a single N-channel metal oxide field-effect transistor (hereinafter, referred to as NMOS) and a capacitor has been put into practical use. This kind of memory has a defect that it takes much time to read information from a memory cell to a data line. This is due to the fact that the data line is connected to the drain electrode of an NMOS within a memory cell.
That is, when a memory cell is selected, the voltage across the capacitance is increased by the influence of the voltage on the data line. Thus, in the NMOS within the cell, the voltage between the source connected to a terminal of this capacitance and the gate connected to a word line is not rapidly increased when the voltage on the word line is increased. Therefore, because of a slight increase of the conductance of NMOS, much time is required for the information within the cell to be completely read therefrom to the data line. This forces the start of a succeeding detecting amplifier operation to be delayed, and thus a large amount of time is taken up before the information in the memory cell is used by the external circuit.
This problem will also occur in the P-channel metal oxide field-effect transistor (hereinafter, referred to as PMOS).